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general description the max15020 high-voltage step-down dc-dc con- verter operates over an input voltage range of 7.5v to 40v. the device integrates a 0.2 high-side switch and is capable of delivering 2a load current with excellent load and line regulation. the output is dynamically adjustable from 0.5v to 36v through the use of an exter- nal reference input (refin). the max15020 consumes only 6a in shutdown mode. the device utilizes feed-forward voltage-mode architec- ture for good noise immunity in the high-voltage switch- ing environment and offers external compensation for maximum flexibility. the switching frequency is selec- table to 300khz or 500khz and can be synchronized to an external clock signal of 100khz to 500khz by using the sync input. the ic features a maximum duty cycle of 95% (typ) at 300khz. the device includes configurable undervoltage lockout (uvlo) and soft-start. protection features include cycle-by-cycle current limit, hiccup-mode for output short-circuit protection, and thermal shutdown. the max15020 is available in a 20-pin tqfn 5mm x 5mm package and is rated for operation over the -40c to +125c temperature range. applications printer head driver power supply automotive power supply industrial power supply step-down power supply features ? wide 7.5v to 40v input voltage range ? 2a output current, up to 96% efficiency ? dynamic programmable output voltage (0.5v to 36v) ? maximum duty cycle of 95% (typ) at 300khz ? 100khz to 500khz synchronizable sync frequency range ? configurable uvlo and soft-start ? low-noise, voltage-mode step-down converter ? programmable output-voltage slew rate ? lossless constant current limit with fixed timeout to hiccup mode ? extremely low-power consumption (< 6? typ) in shutdown mode ? 20-pin (5mm x 5mm) thin qfn package max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming ________________________________________________________________ maxim integrated products 1 ordering information max15020 on/off in dvreg v out (0.5v to 36v) lx refout refin ep ss pwm input v in (7.5v to 40v) bst fb comp sync gnd fsel pgnd reg typical operating circuit 19-0811; rev 1; 5/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package max15020atp+ -40c to +125c 20 tqfn-ep* pin configuration appears at end of data sheet. evaluation kit available
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = 36v, v reg = v dvreg , v pgnd = v gnd = v ep = 0v, v sync = 0v, c refout = 0.1f, t a = t j = -40c to +125c, fsel = reg, unless otherwise noted. typical values are at t a = +25c.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, on/ off to gnd......... ...................................-0.3v to +45v lx to gnd................................................-0.715v to (v in + 0.3v) bst to gnd ..................................................-0.3v to (v in + 12v) bst to lx................................................................-0.3v to +12v pgnd, ep to gnd .................................................-0.3v to +0.3v reg, dvreg, sync to gnd .................................-0.3v to +12v fb, comp, fsel, refin, refout, ss to gnd .............................................-0.3v to (v reg + 0.3v) continuous current through internal power mosfet t j = +125c..........................................................................4a t j = +150c.......................................................................2.7a continuous power dissipation (t a = +70c) thin qfn, single-layer board (5mm x 5mm) (derate 21.3mw/c above +70c) ...........................1702.1mw thin qfn, multilayer board (5mm x 5mm) (derate 34.5mw/c above +70c) ...........................2758.6mw maximum junction temperature .....................................+150c storage temperature range ............................-60c to +150c lead temperature (soldering, 10s) ................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units input voltage range v in 7.5 40.0 v uvlo rising threshold uvlo rising 6.80 7.20 7.45 v uvlo falling threshold uvlo falling 6.0 6.5 7.0 v uvlo hysteresis uvlo hyst 0.7 v quiescent supply current v in = 40v, v fb = 1.3v 1.6 2.8 ma switching supply current v in = 40v, v fb = 0v 14.5 ma shutdown current i shdn v on/ off = 0.2v, v in = 40v 6 15 a on/ off control input-voltage threshold v on/ off v on/ off rising 1.200 1.225 1.270 v input-voltage threshold hysteresis 120 mv input bias current v on/ off = 0v to v in -250 +250 na shutdown threshold voltage v sd 0.2 v internal voltage regulator (reg) output voltage i reg = 0 to 20ma 7.1 8.3 v oscillator v fsel = 0v 450 550 frequency f sw v fsel = v reg 270 330 khz v fsel = 0v 85 maximum duty cycle d max v fsel = v reg 90 % sync/fsel high-level voltage 2 v sync/fsel low-level voltage 0.8 v sync frequency range f sync v fsel = v reg 100 550 khz
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming _______________________________________________________________________________________ 3 note 1: limits are 100% production tested at t a = t j = +25c. limits at -40c and +125c are guaranteed by design. parameter symbol conditions min typ max units soft-start/refin/refout/fb soft-start current i ss 81526a refout output voltage 0.97 0.98 1.01 v refin input range 0 3.6 v refin = refout 0.97 0.98 1.01 v fb accuracy fb = comp, v refin = 0.2v to 3.6v v refin - 5mv v refin v refin + 5mv mv fb input current v ss = 0.2v, v fb = 0v -250 +250 na open-loop gain 80 db unity-gain bandwidth 1.8 mhz f sync = 100khz, v in = 7.5v 9.4 pwm modulator gain (v in / v ramp ) f sync = 500khz, v in = 40v 8.9 v/v current-limit comparator cycle-by-cycle switch current limit i ilim 2.5 3.5 4.5 a number of ilim events to hiccup 4 hiccup timeout 512 clock periods power switch switch on-resistance v bst - v lx = 6v 0.18 0.35 bst leakage current v bst = v lx = v in = 40v 10 a switch leakage current v in = 40v, v lx = v bst = 0v 10 a switch gate charge v bst - v lx = 6v 10 nc thermal shutdown thermal shutdown temperature t shdn +160 c thermal shutdown hysteresis 20 c electrical characteristics (continued) (v in = 36v, v reg = v dvreg , v pgnd = v gnd = v ep = 0v, v sync = 0v, c refout = 0.1f, t a = t j = -40c to +125c, fsel = reg, unless otherwise noted. typical values are at t a = +25c.) (note 1)
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming 4 _______________________________________________________________________________________ typical operating characteristics (v in = 36v, circuit of figure 2, t a = +25c, unless otherwise noted.) undervoltage lockout hysteresis vs. temperature max15020 toc01 temperature ( c) undervoltage lockout hysteresis 110 85 35 60 10 -15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -40 135 on/off threshold hysteresis vs. temperature max15020 toc02 temperature ( c) on/off threshold hysteresis (v) 110 85 35 60 10 -15 0.05 0.10 0.15 0.20 0 -40 135 shutdown supply current vs. input voltage max15020 toc03 input voltage (v) supply current ( a) 30 20 10 1 2 3 4 5 6 7 0 040 no-load supply current vs. input voltage max15020 toc04 input voltage (v) supply current (ma) 30 20 10 2 4 8 6 10 12 14 16 0 040 operating frequency vs. temperature max15020 toc05 temperature ( c) operating frequency (khz) 110 85 35 60 10 -15 290 292 294 296 298 300 302 304 306 308 288 -40 135 maximum duty cycle vs. input voltage max15020 toc06 input voltage (v) duty cycle (%) 30 20 10 86 88 82 84 90 92 94 96 98 100 80 040 loop gain/phase vs. frequency max15020 toc07 frequency (khz) gain (db) phase (degrees) 100 10 1 -40 -30 -20 -10 0 10 20 30 40 50 -50 -144 -108 -72 -36 0 36 72 108 144 180 -180 0.1 1000 phase v in = 37v, v out = 15v, i out = 2.02a gain maximum load current vs. input voltage max15020 toc08 input voltage (v) load current (a) 35 30 20 25 10 15 5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 2.5 040 t a = -45 c t a = +25 c t a = +85 c
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming _______________________________________________________________________________________ 5 turn-on/turn-off waveform max15020 toc10 10ms/div 5v/div 0v 1v/div 0v v out v on/off v in = 40v, r load = 27 refout voltage vs. temperature max15020 toc11 temperature ( c) refout voltage (v) 110 85 60 35 10 -15 0.97 0.99 1.01 1.03 1.05 0.95 -40 135 efficiency vs. load current max15020 toc12 output current (a) efficiency (%) 1 0.1 10 20 30 40 50 60 70 80 90 100 0 0.01 10 v in = 40v v in = 24v f s = 500khz v out = 3.3v v in = 12v v in = 7.5v efficiency vs. load current max15020 toc13 output current (a) efficiency (%) 1 0.1 10 20 30 40 50 60 70 80 90 100 0 0.01 10 f s = 500khz v in = 40v v out = 30v turn-on/turn-off waveform max15020 toc09 10ms/div 5v/div 0v 1v/div 0v v out v on/off v in = 12v, r load = 27 typical operating characteristics (continued) (v in = 36v, circuit of figure 2, t a = +25c, unless otherwise noted.) load transient max15020 toc14 200 s/div 50mv/div ac-coupled 2a 1a i out v out v in = 12v, v out = 3.3v load transient max15020 toc15 200 s/div 50mv/div ac-coupled 1.2a 0.2a v out i out v in = 12v, v out = 3.3v
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming 6 _______________________________________________________________________________________ light-load switching waveforms max15020 toc18 1 s/div 20v/div 0v 1a/div 0a i lx v lx i load = 40ma switching waveforms max15020 toc19 1 s/div 20v/div 0v 1a/div 0a i lx v lx i load = 500ma load transient max15020 toc16 200 s/div 50mv/div ac-coupled 2a 1a i out v out v in = 40v, v out = 30v load transient max15020 toc17 200 s/div 50mv/div ac-coupled 1.1a 0.25a i out v out v in = 40v, v out = 30v typical operating characteristics (continued) (v in = 36v, circuit of figure 2, t a = +25c, unless otherwise noted.) heavy-load switching waveforms max15020 toc20 1 s/div 20v/div 0v 1a/div 0a i lx v lx i load = 2a feedback voltage vs. refin input voltage max15020 toc21 refin input voltage (v) feedback voltage (v) 3 2 1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 04
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v in = 36v, circuit of figure 2, t a = +25c, unless otherwise noted.) soft-start voltage rise vs. refin voltage rise max15020 toc22 v refin dv/dt (v/ms) v ss dv/dt (v/ms) 0.1 1 0.1 1 10 0.01 0.01 10 c ss = 0.1 f c ss = 0.01 f v ss and v out response to refin pwm max15020 toc23 2ms/div 1v 0.5v 0v 0v 20v/div 1v/div 1v/div 0v v pwm v refin v ss v out d = 70% to 100% 10k and 0.1 f rc on refin modulator gain vs. input voltage max15020 toc24 input voltage (v) modulator gain (v/v) 35 30 25 20 15 10 8.5 9.0 9.5 10.0 10.5 11.0 8.0 540 soft-start charge current vs. temperature max15020 toc25 temperature ( c) soft-start charge current ( a) 110 85 35 60 10 -15 14.6 14.7 14.8 14.9 15.0 15.1 15.2 15.3 15.4 15.5 14.5 -40 135
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming 8 _______________________________________________________________________________________ pin description pin name function 1 comp voltage-error-amplifier output. connect comp to the necessary compensation feedback network. 2fb feedback regulation point. connect to the center tap of an external resistor-divider connected between the output and gnd to set the output voltage. the fb voltage regulates to the voltage applied to refin. 3 on/ off on/ off control. the on/ off rising threshold is set to approximately 1.225v. connect to the center tap of a resistive divider connected between in and gnd to set the turn-on (rising) threshold. connect on/ off to gnd to shut down the ic. connect on/ off to in for always-on operation given that v in has risen above the uvlo threshold. on/ off can be used for power-supply sequencing. 4 refout 0.98v reference voltage output. bypass refout to gnd with a 0.1f ceramic capacitor. refout is to be used only with refin. it is not to be used to power any other external circuitry. 5 ss soft-start. connect a 0.01f or greater ceramic capacitor from ss to gnd. see the soft-start (ss) section. 6 refin external reference input. connect to an external reference. v fb regulates to the voltage applied to refin. connect refin to refout to use the internal 1v reference. see the reference input and output (refin, refout) section. 7 fsel internal switching frequency selection input. connect fsel to reg to select f sw = 300khz. connect fsel to gnd to select f sw = 500khz. when an external clock is connected to sync connect fsel to reg. 8 sync oscillator synchronization input. sync can be driven by an external 100khz to 500khz clock to synchronize the max15020s switching frequency. connect sync to gnd to disable the synchronization function. when using sync, connect fsel to reg. 9 dvreg power supply for internal digital circuitry. connect a 10 ? resistor from reg to dvreg. connect dvreg to the anode of the boost diode, d2 in figure 2. bypass dvreg to gnd with at least a 1f ceramic capacitor. 10 pgnd power-ground connection. connect the input filter capacitors negative terminal, the anode of the freewheeling diode, and the output filter capacitors return to pgnd. connect externally to gnd at a single point near the input bypass capacitors return terminal. 11 n.c. no connection. leave unconnected or connect to gnd 12 bst high-side gate driver supply. connect bst to the cathode of the boost diode and to the positive terminal of the boost capacitor. 13, 14, 15 lx source connection of internal high-side switch. connect the inductor and rectifier diodes cathode to lx. 16, 17, 18 in supply input connection. connect to an external voltage source from 7.5v to 40v. 19 reg 8v internal regulator output. bypass to gnd with at least a 1f ceramic capacitor. do not use reg to power external circuitry. 20 gnd ground connection. solder the exposed pad to a large gnd plane. connect gnd and pgnd together at one point near the input bypass capacitor return terminal. ep exposed pad. connect ep to gnd. connecting ep does not remove the requirement for proper ground connections to the appropriate pins. see the pcb layout and routing section.
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming _______________________________________________________________________________________ 9 max15020 on/off enable switching ldo in reg refout refin ss fb comp sync fsel en ref ref thermal shdn overload management logic high-side current sense ref icss ref clk ilim ref_ilim in bst lx dvreg pgnd ssa ok vpok regok e/a cpwm gnd en in osc ramp clk figure 1. functional diagram
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming 10 ______________________________________________________________________________________ max15020 on/off in d2 d1 c4 1 f l1 22 h v out dvreg lx reg refin ss r5 10 r1 97.5k r2 4.02k c1 560 f r7 10k r8 340 c7 0.1 f c11 0.027 f c6 560 f r3 10k c9 0.1 f c2 1 f c10 1 f c3 0.1 f v in 7.5v to 40v pwm input 0 bst r6 10k c13 330pf c12 0.1 f r9 15.8k fb comp c8 0.22 f refout c5 0.1 f sync gnd fsel pgnd ep figure 2. typical application circuit detailed description the max15020 voltage-mode step-down converter contains an internal 0.2 power mosfet switch. the max15020 input voltage range is 7.5v to 40v. the internal low r ds(on) switch allows for up to 2a of out- put current. the external compensation, voltage feed- forward, and automatically adjustable maximum ramp amplitude simplify the loop compensation design allow- ing for a variety of l and c filter components. in shut- down, the supply current is typically 6a. the output voltage is dynamically adjustable from 0.5v to 36v. additional features include an externally programmable uvlo through the on/ off pin, a programmable soft- start, cycle-by-cycle current limit, hiccup-mode output short-circuit protection, and thermal shutdown. internal linear regulator (reg) reg is the output terminal of the 8v ldo powered from in and provides power to the ic. connect reg exter- nally to dvreg to provide power for the internal digital circuitry. place a 1f ceramic bypass capacitor, c2, next to the ic from reg to gnd. during normal opera- tion, reg is intended for powering up only the internal circuitry and should not be used to supply power to the external loads. uvlo/on/ off threshold the max15020 provides a fixed 7v uvlo function which monitors the input voltage (v in ). the device is held off until v in rises above the uvlo threshold. on/ off provides additional turn-on/turn-off control. program the on/ off threshold by connecting a resis- tive divider from in to on/ off to gnd. the device turns on when v on/ off rises above the on/ off thresh- old (1.225v), given that v in has risen above the uvlo threshold. driving on/ off to ground places the ic in shutdown. when in shutdown the internal power mosfet turns off, all internal circuitry shuts down, and the quiescent supply current reduces to 6a (typ.). connect an rc network from on/ off to gnd to set a turn-on delay that can be used to sequence the output voltages of multiple devices.
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming ______________________________________________________________________________________ 11 soft-start (ss) at startup, after v in is applied and the uvlo threshold is reached, a 15a (typ) current is sourced into the capacitor (c ss ) connected from ss to gnd forcing the v ss voltage to ramp up slowly. if v refin is set to a dc voltage or has risen faster than the c ss charge rate, then v ss will stop rising once it reaches v refin . if v refin rises at a slower rate, v ss will follow the v refin voltage rise rate. v out rises at the same rate as v ss since v fb follows v ss . set the soft-start time (t ss ) using following equation: where t ss is in seconds and c ss is in farads. reference input and output (refin, refout) the max15020 features a reference input for the inter- nal error amplifier. the ic regulates fb to the ss voltage which is driven by the dc voltage applied to refin. connect refin to refout to use the internal 0.98v ref- erence. connect refin to a variable dc voltage source to dynamically control the output voltage. alternatively, refin can also be driven by a duty-cycle control pwm source through a lowpass rc filter (figure 2). internal digital power supply (dvreg) dvreg is the supply input for the internal digital power supply. the power for dvreg is derived from the out- put of the internal regulator (reg). connect a 10 resistor from reg to dvreg. bypass dvreg to gnd with at least a 1f ceramic capacitor. error amplifier the output of the internal error amplifier (comp) is available for frequency compensation (see the compensation design section). the inverting input is fb, the noninverting input is ss, and the output is comp. the error amplifier has an 80db open-loop gain and a 1.8mhz gbw product. when an external clock is used, connect fsel to reg. oscillator/synchronization input (sync) with sync connected to gnd, the ic uses the internal oscillator and switches at a fixed frequency of 300khz or 500khz based upon the selection of fsel. for external synchronization, drive sync with an external clock from 100khz to 500khz and connect fsel to reg. when dri- ven with an external clock, the device synchronizes to the rising edge of sync. pwm comparator/voltage feed-forward an internal ramp generator is compared against the output of the error amplifier to generate the pwm sig- nal. the maximum amplitude of the ramp (v ramp ) auto- matically adjusts to compensate for input voltage and oscillator frequency changes. this causes the v in / v ramp to be a constant 9v/v across the input voltage range of 7.5v to 40v and the sync frequency range of 100khz to 500khz. this simplifies loop compensation design by allowing large input voltage ranges and large frequency range selection. output short-circuit protection (hiccup mode) the max15020 protects against an output short circuit by utilizing hiccup-mode protection. in hiccup mode, a series of sequential cycle-by-cycle current-limit events cause the part to shut down and restart with a soft-start sequence. this allows the device to operate with a con- tinuous output short circuit. during normal operation, the switch current is measured cycle-by-cycle. when the current limit is exceeded, the internal power mosfet turns off until the next on-cycle and the hiccup counter increments. if the counter counts four consecutive overcurrent limit events, the device discharges the soft-start capacitor and shuts down for 512 clock periods before restarting with a soft- start sequence. each time the power mosfet turns on and the device does not exceed the current limit, the counter is reset. thermal-overload protection the max15020 features an integrated thermal-over- load protection. thermal-overload protection limits the total power dissipation in the device and protects it in the event of an extended thermal fault condition. when the die temperature exceeds +160c, an internal ther- mal sensor shuts down the part, turning off the power mosfet and allowing the ic to cool. after the temper- ature falls by 20c, the part restarts beginning with the soft-start sequence. t vc a ss refin ss = 15
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming 12 ______________________________________________________________________________________ applications information setting the on/ off threshold when the voltage at on/ off rises above 1.225v, the max15020 turns on. connect a resistive divider from in to on/ off to gnd to set the turn-on voltage (see figure 2). first select the on/ off to the gnd resistor (r2), then calculate the resistor from in to on/ off (r1) using the following equation: where v in is the input voltage at which the converter turns on, v on/ off = 1.225v and r2 is chosen to be less than 600k . if on/ off is connected to in directly, the uvlo feature monitors the supply voltage at in and allows operation to start when v in rises above 7.2v. setting the output voltage connect a resistor-divider from out to fb to gnd to set the output voltage (see figure 2). first calculate the resistor (r7) from out to fb using the guidelines in the compensation design section. once r7 is known, cal- culate r8 using the following equation: where v fb = refin and refin = 0 to 3.6v. setting the output-voltage slew rate the output-voltage rising slew rate tracks the v ss slew rate, given that the control loop is relatively fast com- pared with the v ss slew rate. the maximum v ss upswing slew rate is controlled by the soft-start current charging the capacitor connected from ss to gnd according to the formula below: when driving v ss with a slow-rising voltage source at refin, v out will slowly rise according to the v refin slew rate. the output-voltage falling slew rate is limited to the dis- charge rate of c ss assuming there is enough load cur- rent to discharge the output capacitor at this rate. the c ss discharge current is 15a. if there is no load, then the output voltage falls at a slower rate based upon leakage and additional current drain from c out . inductor selection three key inductor parameters must be specified for operation with the max15020: inductance value (l), peak inductor current (i peak ), and inductor saturation current (i sat ). the minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current ( i l ). higher i l allows for a lower inductor value while a lower i l requires a higher inductor value. a lower inductor value minimizes size and cost and improves large-signal and transient response, but reduces effi- ciency due to higher peak currents and higher peak-to- peak output voltage ripple for the same output capacitor. higher inductance increases efficiency by reducing the ripple current. resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels especially when the induc- tance is increased without also allowing for larger inductor dimensions. a good compromise is to choose i p-p equal to 40% of the full load current. calculate the inductor using the following equation: v in and v out are typical values so that efficiency is optimum for typical conditions. the switching frequen- cy (f sw ) is fixed at 300khz or 500khz and can vary between 100khz and 500khz when synchronized to an external clock (see the oscillator/synchronization input (sync) section). the peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worst at the maximum input voltage. see the output capacitor selection section to verify that the worst-case output ripple is acceptable. the inductor saturating current (i sat ) is also important to avoid runaway cur- rent during continuous output short circuit. select an inductor with an i sat specification higher than the max- imum peak current limit of 4.5a. l vv v vf i in out out in sw l = ? () dv dt rr r dv dt rr r i c out ss ss ss = + = + 78 8 78 8 r r v v out fb 8 7 1 = ? ? ? ? ? ? ? rr v v in on off 12 1 = ? ? ? ? ? ? ? ? ? /
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming ______________________________________________________________________________________ 13 input capacitor selection the discontinuous input current of the buck converter causes large input ripple currents and therefore the input capacitor must be carefully chosen to keep the input-voltage ripple within design requirements. the input-voltage ripple is comprised of v q (caused by the capacitor discharge) and v esr (caused by the esr (equivalent series resistance) of the input capacitor). the total voltage ripple is the sum of v q and v esr . calculate the input capacitance and esr required for a specified ripple using the following equations: where: i out_max is the maximum output current, d is the duty cycle, and f sw is the switching frequency. the max15020 includes internal and external uvlo hysteresis and soft-start to avoid possible unintentional chattering during turn-on. however, use a bulk capaci- tor if the input source impedance is high. use enough input capacitance at lower input voltages to avoid pos- sible undershoot below the uvlo threshold during transient loading. output capacitor selection the allowable output-voltage ripple and the maximum deviation of the output voltage during load steps deter- mine the output capacitance and its esr. the output ripple is mainly composed of v q (caused by the capacitor discharge) and v esr (caused by the volt- age drop across the esr of the output capacitor). the equations for calculating the peak-to-peak output volt- age ripple are: normally, a good approximation of the output-voltage ripple is v ripple v esr + v q . if using ceramic capacitors, assume the contribution to the output-volt- age ripple from esr and the capacitor discharge to be equal to 20% and 80%, respectively. i l is the peak-to- peak inductor current (see the input capacitor selection section) and f sw is the converters switching frequency. the allowable deviation of the output voltage during fast load transients also determines the output capaci- tance, its esr, and its equivalent series inductance (esl). the output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the converter (see the compensation design section). the resistive drop across the output capacitors esr, the drop across the capacitors esl ( v esl ), and the capacitor discharge cause a voltage droop during the load step. use a combination of low-esr tantalum/aluminum elec- trolytic and ceramic capacitors for better transient load and voltage ripple performance. surface-mount capaci- tors and capacitors in parallel help reduce the esl. keep the maximum output-voltage deviations below the tolerable limits of the electronics powered. use the fol- lowing equations to calculate the required esr, esl, and capacitance value during a load step: where i step is the load step, t step is the rise time of the load step, and t response is the response time of the controller. esr v i c it v esl v esr step out step response q e = = = s sl step step t i ? v i cf v esr i q l out sw esr l = = 16 i vv v vf l d v v l in out out in sw out in = = ? () esr v i i c id esr out max l in out max = + ? ? ? ? ? ? = _ _ ( 2 1 1 ? d vf qsw )
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming 14 ______________________________________________________________________________________ compensation design the max15020 uses a voltage-mode control scheme that regulates the output voltage by comparing the error-amplifier output (comp) with an internal ramp to produce the required duty cycle. the output lowpass lc filter creates a double pole at the resonant frequen- cy, which has a gain drop of -40db/decade. the error amplifier must compensate for this gain drop and phase shift to achieve a stable closed-loop system. the basic regulator loop consists of a power modulator, an output feedback divider, and a voltage error amplifi- er. the power modulator has a dc gain set by v in / v ramp , with a double pole and a single zero set by the output inductance (l), the output capacitance (c out ) (c6 in the figure 2) and its esr. the power modulator incorporates a voltage feed-forward feature, which auto- matically adjusts for variations in the input voltage resulting in a dc gain of 9. the following equations define the power modulator: the switching frequency is internally set at 300khz or 500khz, or can vary from 100khz to 500khz when driven with an external sync signal. the crossover frequency (f c ), which is the frequency when the closed-loop gain is equal to unity, should be set as f sw / 2 or lower. the error amplifier must provide a gain and phase bump to compensate for the rapid gain and phase loss from the lc double pole. this is accomplished by utiliz- ing a type 3 compensator that introduces two zeros and three poles into the control loop. the error amplifier has a low-frequency pole (f p1 ) near the origin. in reference to figures 3 and 4, the two zeros are at: and the higher frequency poles are at: compensation when f c < f esr figure 3 shows the error-amplifier feedback as well as its gain response for circuits that use low-esr output capacitors (ceramic). in this case f zesr occurs after f c . f z1 is set to 0.8 x f lc(mod) and f z2 is set to f lc to com- pensate for the gain and phase loss due to the double pole. choose the inductor (l) and output capacitor (c out ) as described in the inductor selection and output capacitor selection sections. choose a value for the feedback resistor r9 in figure 3 (values between 1k and 10k are adequate). c12 is then calculated as: f c occurs between f z2 and f p2 . the error-amplifier gain (g ea ) at f c is due primarily to c11 and r9. therefore, g ea(fc) = 2 x f c x c11 x r9 and the modu- lator gain at f c is: since g ea(fc) x g mod(fc) = 1, c11 is calculated by: f p2 is set at 1/2 the switching frequency (f sw ). r6 is then calculated by: since r7 >> r6, r7 + r6 can be approximated as r7. r7 is then calculated as: f p3 is set at 5 x f c . therefore, c13 is calculated as: c c crf p 13 12 2129 1 3 = ? r fc lc 7 1 211 = r cf sw 6 1 21105 = . c flc rg cout mod dc 11 2 9 = () g g lc f mod fc mod dc out c () () () = 2 22 c fr lc 12 1 208 9 = . f rc and f r cc cc pp 23 1 2611 1 29 12 13 12 1 = = + 3 3 ? ? ? ? ? ? f rc and f rr c zz 12 1 2912 1 26711 = = + () g v v f lc f c mod dc in ramp lc esr out () == = = 9 1 2 1 2 e esr
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming ______________________________________________________________________________________ 15 compensation when f c > f zesr for larger esr capacitors such as tantalum and alu- minum electrolytics, f zesr can occur before f c . if f zesr < f c , then f c occurs between f p2 and f p3 . f z1 and f z2 remain the same as before, however, f p2 is now set equal to f zesr . the output capacitors esr zero fre- quency is higher than f lc but lower than the closed- loop crossover frequency. the equations that define the error amplifiers poles and zeros (f z1 , f z2 , f p1 , f p2 , and f p3 ) are the same as before. however, f p2 is now lower than the closed-loop crossover frequency. figure 4 shows the error-amplifier feedback as well as its gain response for circuits that use higher-esr output capac- itors (tantalum or aluminum electrolytic). pick a value for the feedback resistor r9 in figure 4 (values between 1k and 10k are adequate). c12 is then calculated as: the error-amplifier gain between f p2 and f p3 is approxi- mately equal to r9 / r6 (given that r6 << r7). r6 can then be calculated as: c11 is then calculated as: since r7 >> r6, r7 + r6 can be approximated as r7. r7 is then calculated as: f p3 is set at 5 x f c . therefore, c13 is calculated as: based on the calculations above, the following com- pensation values are recommended when the switch- ing frequency of dc-dc converter ranges from 100khz to 500khz. ( note: the compensation parameters in figure 2 are strongly recommended if the switching frequency is from 300khz to 500khz. ) c c crf p 13 12 2129 1 3 = ? r fc lc 7 1 211 = c c esr r out 11 6 = r rf f lc c 6 910 2 2 = c fr lc 12 1 208 9 = . c12 ss fb f z1 f z2 f c f p2 f p3 closed-loop gain frequency (hz) error- amplifier gain gain (db) c13 c11 r9 v out comp r6 r7 r8 error amplifier figure 3. error-amplifier compensation circuit (closed-loop and error-amplifier gain plot) for ceramic capacitors c12 ss f z1 f z2 f p2 f p3 closed-loop gain error- amplifier gain c13 c11 r9 v out comp r6 r7 r8 error amplifier f c frequency (hz) gain (db) fb figure 4. error-amplifier compensation circuit (closed-loop and error-amplifier gain plot) for higher esr output capacitors
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming 16 ______________________________________________________________________________________ power dissipation the max15020 is available in a thermally enhanced package and can dissipate up to 2.7w at t a = +70c. when the die temperature reaches +160c, the part shuts down and is allowed to cool. after the parts cool by 20c, the device restarts with a soft-start. the power dissipated in the device is the sum of the power dissipated from supply current (p q ), transition losses due to switching the internal power mosfet (p sw ), and the power dissipated due to the rms cur- rent through the internal power mosfet (p mosfet ). the total power dissipated in the package must be lim- ited such that the junction temperature does not exceed its absolute maximum rating of +150c at maxi- mum ambient temperature. calculate the power lost in the max15020 using the following equations: the power loss through the switch: r on is the on-resistance of the internal power mosfet (see the electrical characteristics table). the power loss due to switching the internal mosfet: where t r and t f are the rise and fall times of the internal power mosfet measured at lx. the power loss due to the switching supply current (i sw ): p q = v in x i sw the total power dissipated in the device is: p total = p mosfet + p sw + p q pcb layout and routing use the following guidelines to layout the switching voltage regulator: 1) place the in and dvreg bypass capacitors close to the max15020 pgnd pin. place the reg bypass capacitor close to the gnd pin. 2) minimize the area and length of the high-current loops from the input capacitor, switching mosfet, inductor, and output capacitor back to the input capacitor negative terminal. 3) keep short the current loop formed by the switch- ing mosfet, schottky diode, and input capaci- tor. 4) keep gnd and pgnd isolated and connect them at one single point close to the negative terminal of the input filter capacitor. 5) place the bank of output capacitors close to the load. 6) distribute the power components evenly across the board for proper heat dissipation. 7) provide enough copper area at and around the max15020 and the inductor to aid in thermal dis- sipation. 8) use 2oz copper to keep the trace inductance and resistance to a minimum. thin copper pcbs can compromise efficiency since high currents are involved in the application. also, thicker copper conducts heat more effectively, thereby reducing thermal impedance. 9) place enough vias in the pad for the ep of the max15020 so that the heat generated inside can be effectively dissipated by pcb copper. p vi tt f sw in out r f sw = () 4 pi r iii mosfet rms mosfet on rms mosfet pk = =+ + _ _ 2 2 p pk pk pk pk out l pk ii d ii i ii + + () + ? ? ? ? =+ = ?? ? 3 2 o out l i ? 2
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming ______________________________________________________________________________________ 17 max15020 thin qfn (5mm x 5mm) top view 19 20 18 17 7 6 8 fb refout ss 9 comp lx bst n.c. lx 12 in 45 15 14 12 11 + reg gnd dvreg sync fsel refin on/off lx 3 13 in 16 10 pgnd in pin configuration chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 20 tqfn-ep t2055+5 21-0140 90-0010
max15020 2a, 40v step-down dc-dc converter with dynamic output-voltage programming maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/07 initial release 1 5/11 corrected the feedback resistor reference from r6 to r9 in the compensation when f c < f esr section 14

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